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authorChristian Cunningham <cc@localhost>2022-03-24 09:38:08 -0700
committerChristian Cunningham <cc@localhost>2022-03-24 09:38:08 -0700
commit93bf62580a68533dc8252b9a2a055c02f34ecb67 (patch)
tree1b1ca92ebbe107a998136a1442c0dba5be885e13 /kernel/sys/core.c
parent3e64dda5d5c350cc325650133f7e64967f1efe84 (diff)
Modularized
Diffstat (limited to 'kernel/sys/core.c')
-rw-r--r--kernel/sys/core.c58
1 files changed, 58 insertions, 0 deletions
diff --git a/kernel/sys/core.c b/kernel/sys/core.c
new file mode 100644
index 0000000..d76b712
--- /dev/null
+++ b/kernel/sys/core.c
@@ -0,0 +1,58 @@
+#include <cpu/irq.h>
+#include <cpu.h>
+#include <drivers/uart.h>
+#include <globals.h>
+#include <graphics/lfb.h>
+#include <lib/kmem.h>
+#include <lib/mmu.h>
+#include <lib/strings.h>
+#include <symbols.h>
+#include <sys/core.h>
+#include <sys/power.h>
+#include <sys/schedule.h>
+#include <util/mutex.h>
+#include <util/status.h>
+#include <util/time.h>
+
+// Initialize IRQs
+void sysinit(void)
+{
+ // Initialize System Globals
+ stimeh = *(unsigned long*)SYS_TIMER_CHI;
+ stimel = *(unsigned long*)SYS_TIMER_CLO;
+ *(unsigned long*) SYS_TIMER_C0 = 2000000 + stimeh; // 2 second trigger
+ uart_init();
+ ///...
+
+ // Route GPU interrupts to Core 0
+ store32(0x00, GPU_INTERRUPTS_ROUTING);
+
+ // Mask Overrun of UART0
+ store32(1<<4, UART0_IMSC);
+ // Enable UART GPU IRQ
+ store32(1<<25, IRQ_ENABLE2);
+ // Enable Timer
+ //// Get the frequency
+ cntfrq = read_cntfrq();
+ // Clear cntv interrupt and set next 1 second timer
+ write_cntv_tval(cntfrq);
+ // Route timer to core0 fiq
+ routing_core0cntv_to_core0fiq();
+ // Enable timer
+ enablecntv();
+ // Enable system timer
+ store32(SYS_TIMER_SC_M0, IRQ_ENABLE1);
+
+ // Graphics Initialize
+ lfb_init();
+ lfb_showpicture();
+
+ // Initialize Memory Management Unit
+ mmu_init();
+
+ // Initialize Mutex Manager
+ mutex_init();
+
+ // Start Scheduler
+ init_scheduler();
+}