From 9a9331a96509771d7d80e65039021613ba7b3601 Mon Sep 17 00:00:00 2001
From: Christian Cunningham <cc@localhost>
Date: Thu, 20 Jan 2022 23:48:49 -0700
Subject: Markdown list

---
 README.md | 44 ++++++++++++++++++++++----------------------
 1 file changed, 22 insertions(+), 22 deletions(-)

diff --git a/README.md b/README.md
index b714673..8419564 100644
--- a/README.md
+++ b/README.md
@@ -18,34 +18,34 @@
 - // MODE REGISTERS: https://developer.arm.com/documentation/ddi0406/c/System-Level-Architecture/The-System-Level-Programmers--Model/ARM-processor-modes-and-ARM-core-registers/ARM-core-registers?lang=en
 
 ## Todo
-Implement Scheduler for IRQ
-Fix mutex with scheduler
-Implement handlers
-Put threads in user mode
+- Implement Scheduler for IRQ
+- Fix mutex with scheduler
+- Implement handlers
+- Put threads in user mode
 
 
-Note: SYS and USER share registers but differ in privlige
+Note: SYS and USER share registers but differ in privilege
 
 
 # Modes
-From https://developer.arm.com/documentation/den0013/d/ARM-Processor-Modes-and-Registers
-User: 10000 PL0
-FIQ : 10001 PL1
-IRQ : 10010 PL1
-SVC : 10011 PL1
-ABT : 10111 PL1
-UND : 11011 PL1
-SYS : 11111 PL1
+- From https://developer.arm.com/documentation/den0013/d/ARM-Processor-Modes-and-Registers
+- User: 10000 PL0
+- FIQ : 10001 PL1
+- IRQ : 10010 PL1
+- SVC : 10011 PL1
+- ABT : 10111 PL1
+- UND : 11011 PL1
+- SYS : 11111 PL1
 
 # Registers
-From https://developer.arm.com/documentation/ddi0406/c/System-Level-Architecture/The-System-Level-Programmers--Model/ARM-processor-modes-and-ARM-core-registers/ARM-core-registers?lang=en
-User: r0-12_usr,sp_usr,lr_usr,CPSR
-FIQ: r8-r12_fiq,sp_fiq,lr_fiq,SPSR_fiq
-IRQ: sp_irq,lr_irq,SPSR_irq
-SVC: sp_svc,lr_svc,SPSR_svc
-ABT: sp_abt,lr_abt,SPSR_abt
-UND: sp_und,lr_und,SPSR_und
-SYS: Same as user
+- From https://developer.arm.com/documentation/ddi0406/c/System-Level-Architecture/The-System-Level-Programmers--Model/ARM-processor-modes-and-ARM-core-registers/ARM-core-registers?lang=en
+- User: r0-12_usr,sp_usr,lr_usr,CPSR
+- FIQ: r8-r12_fiq,sp_fiq,lr_fiq,SPSR_fiq
+- IRQ: sp_irq,lr_irq,SPSR_irq
+- SVC: sp_svc,lr_svc,SPSR_svc
+- ABT: sp_abt,lr_abt,SPSR_abt
+- UND: sp_und,lr_und,SPSR_und
+- SYS: Same as user
 
 # Program Status Registers
-https://developer.arm.com/documentation/ddi0406/c/System-Level-Architecture/The-System-Level-Programmers--Model/ARM-processor-modes-and-ARM-core-registers/Program-Status-Registers--PSRs-?lang=en#CIHJBHJA
+- https://developer.arm.com/documentation/ddi0406/c/System-Level-Architecture/The-System-Level-Programmers--Model/ARM-processor-modes-and-ARM-core-registers/Program-Status-Registers--PSRs-?lang=en#CIHJBHJA
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