From 49bd4c133fc83de1cb1761ff089a2de03699d991 Mon Sep 17 00:00:00 2001 From: Christian Cunningham Date: Thu, 24 Mar 2022 16:44:51 -0700 Subject: IRQ Subscription --- kernel/sys/core.c | 38 ++++++++++++++++++++------------------ 1 file changed, 20 insertions(+), 18 deletions(-) (limited to 'kernel/sys') diff --git a/kernel/sys/core.c b/kernel/sys/core.c index d76b712..7f42d6e 100644 --- a/kernel/sys/core.c +++ b/kernel/sys/core.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -18,30 +19,30 @@ void sysinit(void) { // Initialize System Globals - stimeh = *(unsigned long*)SYS_TIMER_CHI; - stimel = *(unsigned long*)SYS_TIMER_CLO; - *(unsigned long*) SYS_TIMER_C0 = 2000000 + stimeh; // 2 second trigger + //stimeh = *(unsigned long*)SYS_TIMER_CHI; + //stimel = *(unsigned long*)SYS_TIMER_CLO; + //*(unsigned long*) SYS_TIMER_C0 = 2000000 + stimeh; // 2 second trigger uart_init(); ///... // Route GPU interrupts to Core 0 store32(0x00, GPU_INTERRUPTS_ROUTING); - // Mask Overrun of UART0 - store32(1<<4, UART0_IMSC); - // Enable UART GPU IRQ - store32(1<<25, IRQ_ENABLE2); - // Enable Timer - //// Get the frequency - cntfrq = read_cntfrq(); - // Clear cntv interrupt and set next 1 second timer - write_cntv_tval(cntfrq); - // Route timer to core0 fiq - routing_core0cntv_to_core0fiq(); - // Enable timer - enablecntv(); - // Enable system timer - store32(SYS_TIMER_SC_M0, IRQ_ENABLE1); + //// Mask Overrun of UART0 + //store32(1<<4, UART0_IMSC); + //// Enable UART GPU IRQ + //store32(1<<25, IRQ_ENABLE2); + //// Enable Timer + ////// Get the frequency + //cntfrq = read_cntfrq(); + //// Clear cntv interrupt and set next 1 second timer + //write_cntv_tval(cntfrq); + //// Route timer to core0 fiq + //routing_core0cntv_to_core0fiq(); + //// Enable timer + //enablecntv(); + //// Enable system timer + //store32(SYS_TIMER_SC_M0, IRQ_ENABLE1); // Graphics Initialize lfb_init(); @@ -55,4 +56,5 @@ void sysinit(void) // Start Scheduler init_scheduler(); + add_thread(main, 0, 0); } -- cgit v1.2.1