1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
|
#ifndef CPU_H
#define CPU_H
extern void _start(void);
static inline unsigned long getmode(void)
{
unsigned long mode;
asm volatile ("mrs %0, cpsr" : "=r"(mode));
return mode;
}
static inline void setsvc(void)
{
asm volatile ( "cps #0x13" );
}
static inline void setmode(unsigned long mode)
{
asm volatile ("msr cpsr_c, %0" :: "r"(mode));
}
static inline void* getsysstack(void)
{
void* sp;
asm volatile (
"mrs r0, cpsr\n"
"bic r1, r0, #0x1F\n"
"orr r1, r1, #0x1F\n"
"msr cpsr_c, r1\n"
"mov %0, sp\n"
"msr cpsr_c, r0"
: "=r"(sp));
return sp;
}
static inline void* getsvcstack(void)
{
void* sp;
asm volatile (
"mrs r0, cpsr\n"
"bic r1, r0, #0x1F\n"
"orr r1, r1, #0x13\n"
"msr cpsr_c, r1\n"
"mov %0, sp\n"
"msr cpsr_c, r0"
: "=r"(sp));
return sp;
}
static inline void* getfiqstack(void)
{
void* sp;
asm volatile (
"mrs r0, cpsr\n"
"bic r1, r0, #0x1F\n"
"orr r1, r1, #0x11\n"
"msr cpsr_c, r1\n"
"mov %0, sp\n"
"msr cpsr_c, r0"
: "=r"(sp));
return sp;
}
static inline void* getirqstack(void)
{
void* sp;
asm volatile (
"mrs r0, cpsr\n"
"bic r1, r0, #0x1F\n"
"orr r1, r1, #0x12\n"
"msr cpsr_c, r1\n"
"mov %0, sp\n"
"msr cpsr_c, r0"
: "=r"(sp));
return sp;
}
#define syscall_h_quote(text) #text
#define syscall_h_expand_and_quote(text) syscall_h_quote(text)
#define sys0(sys_n) asm volatile("svc #" syscall_h_expand_and_quote(sys_n) ::: "r0", "r1", "r2", "r3");
#define sys0_64(sys_n,addr) asm volatile("svc #" syscall_h_expand_and_quote(sys_n) "\nmov r2, %0\nstr r1, [r2]\nstr r0, [r2, #4]" ::"r"(addr): "r0", "r1", "r2", "r3", "memory");
#define sys1(sys_n,arg0) asm volatile("svc #" syscall_h_expand_and_quote(sys_n) ::[r0]"r"(arg0): "r0", "r1", "r2", "r3");
#define SYS_YIELD 0
#define SYS_TIME 1
#define SYS_SCHED 2
#define SYS_FREE_STACK 3
#endif
|
