From 91d0ae783e51062f77b120b05c97cd352b9b86d5 Mon Sep 17 00:00:00 2001 From: Christian Cunningham Date: Wed, 17 Aug 2022 22:14:15 -0700 Subject: Initial commit --- src/_arch/arm/asm.rs | 9 +++++ src/_arch/arm/cpu.rs | 10 ++++++ src/_arch/arm/cpu/boot.rs | 12 +++++++ src/_arch/arm/cpu/boot.s | 84 +++++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 115 insertions(+) create mode 100644 src/_arch/arm/asm.rs create mode 100644 src/_arch/arm/cpu.rs create mode 100644 src/_arch/arm/cpu/boot.rs create mode 100644 src/_arch/arm/cpu/boot.s (limited to 'src/_arch/arm') diff --git a/src/_arch/arm/asm.rs b/src/_arch/arm/asm.rs new file mode 100644 index 0000000..c400f2f --- /dev/null +++ b/src/_arch/arm/asm.rs @@ -0,0 +1,9 @@ +//! Wrapping ARMv7-A Instructions + +/// WFE +/// #[inline(always)] +pub fn wfe() { + unsafe { + core::arch::asm!("wfe", options(nomem, nostack)) + } +} diff --git a/src/_arch/arm/cpu.rs b/src/_arch/arm/cpu.rs new file mode 100644 index 0000000..1ca6fab --- /dev/null +++ b/src/_arch/arm/cpu.rs @@ -0,0 +1,10 @@ +//! Architectural processor code. +mod asm; +pub use asm::*; + +/// Pause execution +pub fn wait_forever() -> ! { + loop { + asm::wfe() + } +} diff --git a/src/_arch/arm/cpu/boot.rs b/src/_arch/arm/cpu/boot.rs new file mode 100644 index 0000000..9ea2330 --- /dev/null +++ b/src/_arch/arm/cpu/boot.rs @@ -0,0 +1,12 @@ +//! Architectural boot code +//! # Boot code for ARM +//! crate::cpu::boot::arch_boot + +use core::arch::global_asm; +global_asm!(include_str!("boot.s")); + +/// The Rust entry of the `kernel` binary. +#[no_mangle] +pub unsafe fn _start_rust() -> ! { + crate::kernel_init() +} diff --git a/src/_arch/arm/cpu/boot.s b/src/_arch/arm/cpu/boot.s new file mode 100644 index 0000000..fd2a652 --- /dev/null +++ b/src/_arch/arm/cpu/boot.s @@ -0,0 +1,84 @@ +.equ _core_id_mask, 0b11 +.section .text.boot + +.global _start +_start: +reset: + cpsid aif + mrc p15, #0, r1, c0, c0, #5 + and r1, r1, #_core_id_mask + cmp r1, #1 + beq core1run + cmp r1, #2 + beq core2run + cmp r1, #3 + beq core3run + + ldr r0, =vector + mcr p15, 0, r0, c12, c0, 0 + cps #0x12 + ldr sp, =core0_irq_stack + cps #0x11 + ldr sp, =core0_fiq_stack + cps #0x1B + ldr sp, =core0_undefined_stack + cps #0x17 + ldr sp, =core0_data_stack + cps #0x1f + ldr sp, =core0_sys_stack + cps #0x13 + ldr sp, =core0_svc_stack + + ldr r4, =__bss_start + ldr r9, =__bss_end + mov r5, #0 + mov r6, #0 + mov r7, #0 + mov r8, #0 + b 2f +1: + stmia r4!, {{r5-r8}} +2: + cmp r4, r9 + blo 1b + + ldr r3, =_start_rust + blx r3 + +core1run: +core2run: +core3run: +.global io_halt +undefined: +io_halt: + wfi + b io_halt + +.align 5 +vector: + ldr pc, reset_handler + ldr pc, undefined_handler + ldr pc, undefined_handler + ldr pc, undefined_handler + ldr pc, undefined_handler + ldr pc, undefined_handler + ldr pc, undefined_handler + ldr pc, undefined_handler + +reset_handler: .word reset +undefined_handler: .word undefined + +.section .bss.sysstacks +.align 4 + .space 4096 +core0_undefined_stack: + .space 4096 +core0_svc_stack: + .space 4096 +core0_data_stack: + .space 4096 +core0_irq_stack: + .space 4096 +core0_fiq_stack: + .space 4096 +core0_sys_stack: -- cgit v1.2.1