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authorChristian Cunningham <cc@localhost>2022-03-25 12:34:00 -0700
committerChristian Cunningham <cc@localhost>2022-03-25 12:34:00 -0700
commit357102ee9ccaea7e26c95e409c4c364a63aed423 (patch)
tree04f26bac4f3ed3244a32b33b763049fc7c97f707 /kernel
parent667e5e8cf02e3d5c530d76fa1921bafdd460b70c (diff)
19200 baud over 3MHz
Diffstat (limited to 'kernel')
-rw-r--r--kernel/cpu/irq.c1
-rw-r--r--kernel/drivers/uart.c4
2 files changed, 3 insertions, 2 deletions
diff --git a/kernel/cpu/irq.c b/kernel/cpu/irq.c
index 09b3346..f718b7e 100644
--- a/kernel/cpu/irq.c
+++ b/kernel/cpu/irq.c
@@ -114,6 +114,7 @@ unsigned long c_fiq_handler(void)
if (source & (1 << 3) && irqs[LOCAL_TIMER_IRQ].handler != 0) {
add_thread(irqs[LOCAL_TIMER_IRQ].handler, 0, 1);
write_cntv_tval(cntfrq);
+ return 1;
}
return 0;
}
diff --git a/kernel/drivers/uart.c b/kernel/drivers/uart.c
index 2107a6f..33f9e82 100644
--- a/kernel/drivers/uart.c
+++ b/kernel/drivers/uart.c
@@ -31,8 +31,8 @@ void uart_init(void)
// Clear pending interrupts
store32(0x7FF, UART0_ICR);
// Set to 3Mhz
- store32(10, UART0_IBRD);
- store32(20, UART0_FBRD);
+ store32(9, UART0_IBRD);
+ store32(49, UART0_FBRD);
// Enable FIFO and 8 bit transmission
store32((1<<4)|(1<<5)|(1<<6), UART0_LCRH);
// Mask all interrupts