diff options
| author | Christian Cunningham <cc@localhost> | 2021-12-02 23:17:41 -0700 |
|---|---|---|
| committer | Christian Cunningham <cc@localhost> | 2021-12-02 23:17:41 -0700 |
| commit | 733a45d82e84de894be0c3d29b3305219827f448 (patch) | |
| tree | 26317833fd1dcd25ee348692f6f86cfada2230c9 /src/boot.S | |
| parent | 9a38691f8635c7cbac413cd7f54e5105ca9cb464 (diff) | |
Initial Commit
Diffstat (limited to 'src/boot.S')
| -rw-r--r-- | src/boot.S | 122 |
1 files changed, 61 insertions, 61 deletions
@@ -6,100 +6,100 @@ _start: reset: - // disable core0,1,2. - mrc p15, #0, r1, c0, c0, #5 - and r1, r1, #3 - cmp r1, #0 - bne io_halt + // disable core0,1,2. + mrc p15, #0, r1, c0, c0, #5 + and r1, r1, #3 + cmp r1, #0 + bne io_halt - // set vector address. - ldr r0, =vector - mcr p15, 0, r0, c12, c0, 0 + // set vector address. + ldr r0, =vector + mcr p15, 0, r0, c12, c0, 0 - // save cpsr. - mrs r0, cpsr + // save cpsr. + mrs r0, cpsr - // setup sp in IRQ mode. - bic r1, r0, #0x1f - orr r1, r1, #0x12 - msr cpsr_c,r1 - mov sp,#0x4000 + // setup sp in IRQ mode. + bic r1, r0, #0x1f + orr r1, r1, #0x12 + msr cpsr_c,r1 + mov sp,#0x4000 - // restore cpsr. - msr cpsr_c, r0 + // restore cpsr. + msr cpsr_c, r0 - // setup the stack in SVC mode. - mov sp, #0x8000 + // setup the stack in SVC mode. + mov sp, #0x8000 - // Clear out bss. - ldr r4, =__bss_start - ldr r9, =__bss_end - mov r5, #0 - mov r6, #0 - mov r7, #0 - mov r8, #0 - b 2f + // Clear out bss. + ldr r4, =__bss_start + ldr r9, =__bss_end + mov r5, #0 + mov r6, #0 + mov r7, #0 + mov r8, #0 + b 2f 1: - // store multiple at r4. - stmia r4!, {r5-r8} + // store multiple at r4. + stmia r4!, {r5-r8} - // If we are still below bss_end, loop. + // If we are still below bss_end, loop. 2: - cmp r4, r9 - blo 1b + cmp r4, r9 + blo 1b - // Call kernel_main - ldr r3, =kernel_main - blx r3 + // Call kernel_main + ldr r3, =kernel_main + blx r3 irq: - push {r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,lr} - bl a_irq_handler - pop {r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,lr} - subs pc, lr, #4 + push {r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,lr} + bl a_irq_handler + pop {r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,lr} + subs pc, lr, #4 fiq: - push {r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,lr} - bl a_fiq_handler - pop {r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,lr} - subs pc, lr, #4 + push {r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,lr} + bl a_fiq_handler + pop {r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,lr} + subs pc, lr, #4 .globl io_halt io_halt: - wfi - b io_halt + wfi + b io_halt .globl enable_irq enable_irq: - cpsie i - bx lr + cpsie i + bx lr .globl disable_irq disable_irq: - cpsid i - bx lr + cpsid i + bx lr .globl enable_fiq enable_fiq: - cpsie f - bx lr + cpsie f + bx lr .globl disable_fiq disable_fiq: - cpsid f - bx lr + cpsid f + bx lr .align 5 vector: - ldr pc, reset_handler - ldr pc, undefined_handler - ldr pc, swi_handler - ldr pc, prefetch_handler - ldr pc, data_handler - ldr pc, unused_handler - ldr pc, irq_handler - ldr pc, fiq_handler + ldr pc, reset_handler + ldr pc, undefined_handler + ldr pc, swi_handler + ldr pc, prefetch_handler + ldr pc, data_handler + ldr pc, unused_handler + ldr pc, irq_handler + ldr pc, fiq_handler reset_handler: .word reset undefined_handler: .word io_halt |