aboutsummaryrefslogtreecommitdiff
path: root/src/sys/core.c
blob: f3699d8dd4ac4570803b38c1ce015bd3450cf762 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
#include "../cpu/irq.h"
#include "../drivers/uart.h"
#include "../graphics/lfb.h"
#include "../graphics/drawer.h"
#include "../lib/mem.h"
#include "../lib/strings.h"
#include "../util/time.h"
#include "../util/mutex.h"
#include "../sys/core.h"
#include "../sys/timer.h"
#include "../sys/power.h"

//extern void init_graphics(void);

#ifndef VERSION
char* os_info_v = "?";
#else
char* os_info_v = VERSION;
#endif

static char* irq_on  = " \033[92mEnabled\033[0m";
static char* irq_off = " \033[91mDisabled\033[0m";

// Initialize IRQs
void sysinit() {
	// Mask Overrun of UART0
	store32(1<<4, UART0_IMSC);

	// Enable UART GPU IRQ
	store32(1<<25, IRQ_ENABLE2);

	// Route GPU interrupts to Core 0
	store32(0x00, GPU_INTERRUPTS_ROUTING);
	//*(unsigned long*)

	// Enable Timer
	// As an IRQ
	store32(1<<0, IRQ_BASIC_ENABLE);
	// As a  FIQ
	//store32(0xC0, FIQ_CONTROL);
	// Get the frequency
	cntfrq = read_cntfrq();
	// Clear cntv interrupt and set next 1 second timer
	write_cntv_tval(cntfrq);
	// Route timer to core0 irq
	routing_core0cntv_to_core0irq();
	// Enable timer
	enable_cntv();

	// Graphics Initialize
	//init_graphics();
	//draw_box(0x01FE, 0, 0, 640, 480);
	//draw_box(0xFFFF, 2, 2, 10, 10);
	lfb_init();
	lfb_showpicture();

	// Enable IRQ & FIQ
	enableirq();
	enablefiq();
}

// Checks IRQ status
void chk_irq_stat() {
	uart_string((char*)"Checking Enabled Services...\n");

	// Basic IRQ
	unsigned long ib_val = load32(IRQ_BASIC_ENABLE);
	uart_string((char*)"IRQB Status: ");
	uart_hexn(ib_val);

	// IRQ 1
	unsigned long i1_val = load32(IRQ_ENABLE1);
	uart_string((char*)"IRQ1 Status: ");
	uart_hexn(i1_val);

	// IRQ 2
	unsigned long i2_val = load32(IRQ_ENABLE2);
	uart_string((char*)"IRQ2 Status: ");
	uart_hexn(i2_val);

	// Check UART IRQ
	uart_string((char*)" UART:");
	if (i2_val & (1<<25)) {
		uart_string(irq_on);
	} else {
		uart_string(irq_off);
	}
	uart_char(0x0a);

	// Check TIMER IRQ
	uart_string((char*)" TIMER:");
	if (ib_val & (1<<0)) {
		uart_string(irq_on);
		// Output the frequency
		uart_string((char*)"  Frequency: ");
		cntfrq = read_cntfrq();
		//uart_hexn(cntfrq);
		uart_10(cntfrq);
		uart_string((char*)" Hz\n");
	} else {
		uart_string(irq_off);
	}
	uart_char(0x0a);

	// Check FIQ
	unsigned long f_val = load32(FIQ_CONTROL);
	uart_string((char*)"FIQ Status: ");
	uart_hexn(f_val);
	if (f_val & 0x80) {
		uart_string(irq_on);
	} else {
		uart_string(irq_off);
	}
	uart_char(0x0a);

	// Check GPU Interrupt Routing
	unsigned long g_val = load32(GPU_INTERRUPTS_ROUTING);
	uart_string((char*)"GPU IRQ Routed to Core ");
	uart_char(0x30 + (g_val & 0x3));
	uart_char(0x0a);
	uart_string((char*)"GPU FIQ Routed to Core ");
	uart_char(0x30 + ((g_val>>2) & 0x3));
	uart_char(0x0a);

	uart_char(0x0a);
}

void output_irq_status(void) {
	// Basic IRQ
	unsigned long ib_val = load32(IRQ_BASIC_ENABLE);
	// IRQ 1
	unsigned long i1_val = load32(IRQ_ENABLE1);
	// IRQ 2
	unsigned long i2_val = load32(IRQ_ENABLE2);
	// FIQ
	unsigned long f_val = load32(FIQ_CONTROL);

	uart_string("\033[5;1H");
	// Check GPU Interrupt Routing
	unsigned long g_val = load32(GPU_INTERRUPTS_ROUTING);
	uart_string((char*)"GPU IRQ: Core ");
	uart_char(0x30 + (g_val & 0x3));
	uart_string((char*)" | GPU FIQ: Core ");
	uart_char(0x30 + ((g_val>>2) & 0x3));
	write_string(&g_Drawer, "GPU IRQ: Core ");
	write_hex32(&g_Drawer, g_val & 0b11);
	write_string(&g_Drawer, " | GPU FIQ: Core ");
	write_hex32(&g_Drawer, (g_val >> 2) & 0b11);

	write_string(&g_Drawer, "\n");
	write_hex32(&g_Drawer, ib_val);
	write_string(&g_Drawer, " ");
	write_hex32(&g_Drawer, i1_val);
	write_string(&g_Drawer, " ");
	write_hex32(&g_Drawer, i2_val);
	write_string(&g_Drawer, " ");
	write_hex32(&g_Drawer,  f_val);

	// Check UART IRQ
	write_string(&g_Drawer, "\nUART: ");
	if (i2_val & (1<<25)) {
		uart_string(irq_on);
		write_cstring(&g_Drawer, "Enabled", 0x00FF00);
	} else {
		uart_string(irq_off);
		write_cstring(&g_Drawer, "Disabled", 0xFF0000);
	}
	// Check TIMER IRQ
	write_string(&g_Drawer, "\n");
	write_string(&g_Drawer, "TIMER: ");
	if (ib_val & (1<<0)) {
		uart_string(irq_on);
		write_cstring(&g_Drawer, "Enabled", 0x00FF00);
		// Output the frequency
		uart_string(" @ ");
		unsigned long frq = read_cntfrq()/1000;
		uart_10(frq);
		uart_string((char*)" kHz");
	} else {
		uart_string(irq_off);
		write_cstring(&g_Drawer, "Disabled", 0xFF0000);
	}

}

void postinit() {
	// OS Info
	uart_string("\033[2J\033[1;1H\033[91mDendritOS \033[96mv");
	uart_string(os_info_v);
	uart_string("\033[0m #");
	if (lock_mutex(&exe_cnt_m, SYS_PID) == 0) {
		uart_10(*(exe_cnt_m.addr));
		release_mutex(&exe_cnt_m, SYS_PID);
	}
	// Commands
	uart_string("\033[2;1HMonitor: Ctrl-A m\033[2;20HExit: Ctrl-A x");
	uart_string("\033[3;1HTimer:   Ctrl-T\033[3;20H");
	// Timer Status
	uart_string("\033[4;1HTimer: \033[92mEnabled\033[0m");
	// GPU IRQ Statuses
	output_irq_status();
	// Input line
	uart_string("\033[8;1H> ");
}