diff options
| author | Christian Cunningham <cc@localhost> | 2022-01-20 23:48:49 -0700 |
|---|---|---|
| committer | Christian Cunningham <cc@localhost> | 2022-01-20 23:48:49 -0700 |
| commit | 9a9331a96509771d7d80e65039021613ba7b3601 (patch) | |
| tree | 29d3ae9124727bdda4b249483e2c7ec503fdad60 | |
| parent | 1cb722f199499c0bcfe3a43802593b54ad7f69f6 (diff) | |
Markdown list
| -rw-r--r-- | README.md | 44 |
1 files changed, 22 insertions, 22 deletions
@@ -18,34 +18,34 @@ - // MODE REGISTERS: https://developer.arm.com/documentation/ddi0406/c/System-Level-Architecture/The-System-Level-Programmers--Model/ARM-processor-modes-and-ARM-core-registers/ARM-core-registers?lang=en ## Todo -Implement Scheduler for IRQ -Fix mutex with scheduler -Implement handlers -Put threads in user mode +- Implement Scheduler for IRQ +- Fix mutex with scheduler +- Implement handlers +- Put threads in user mode -Note: SYS and USER share registers but differ in privlige +Note: SYS and USER share registers but differ in privilege # Modes -From https://developer.arm.com/documentation/den0013/d/ARM-Processor-Modes-and-Registers -User: 10000 PL0 -FIQ : 10001 PL1 -IRQ : 10010 PL1 -SVC : 10011 PL1 -ABT : 10111 PL1 -UND : 11011 PL1 -SYS : 11111 PL1 +- From https://developer.arm.com/documentation/den0013/d/ARM-Processor-Modes-and-Registers +- User: 10000 PL0 +- FIQ : 10001 PL1 +- IRQ : 10010 PL1 +- SVC : 10011 PL1 +- ABT : 10111 PL1 +- UND : 11011 PL1 +- SYS : 11111 PL1 # Registers -From https://developer.arm.com/documentation/ddi0406/c/System-Level-Architecture/The-System-Level-Programmers--Model/ARM-processor-modes-and-ARM-core-registers/ARM-core-registers?lang=en -User: r0-12_usr,sp_usr,lr_usr,CPSR -FIQ: r8-r12_fiq,sp_fiq,lr_fiq,SPSR_fiq -IRQ: sp_irq,lr_irq,SPSR_irq -SVC: sp_svc,lr_svc,SPSR_svc -ABT: sp_abt,lr_abt,SPSR_abt -UND: sp_und,lr_und,SPSR_und -SYS: Same as user +- From https://developer.arm.com/documentation/ddi0406/c/System-Level-Architecture/The-System-Level-Programmers--Model/ARM-processor-modes-and-ARM-core-registers/ARM-core-registers?lang=en +- User: r0-12_usr,sp_usr,lr_usr,CPSR +- FIQ: r8-r12_fiq,sp_fiq,lr_fiq,SPSR_fiq +- IRQ: sp_irq,lr_irq,SPSR_irq +- SVC: sp_svc,lr_svc,SPSR_svc +- ABT: sp_abt,lr_abt,SPSR_abt +- UND: sp_und,lr_und,SPSR_und +- SYS: Same as user # Program Status Registers -https://developer.arm.com/documentation/ddi0406/c/System-Level-Architecture/The-System-Level-Programmers--Model/ARM-processor-modes-and-ARM-core-registers/Program-Status-Registers--PSRs-?lang=en#CIHJBHJA +- https://developer.arm.com/documentation/ddi0406/c/System-Level-Architecture/The-System-Level-Programmers--Model/ARM-processor-modes-and-ARM-core-registers/Program-Status-Registers--PSRs-?lang=en#CIHJBHJA |